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acpl-c78a, acpl-c780, acpl-c784 miniature isolation amplifers data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. note: a 0.1 f bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8. description the acpl-c78a/c780/c784 family of isolation ampli - fers is designed for current sensing in electronic motor drives. in a typical implementation, motor currents fow through an external resistor and the resulting analog voltage drop is sensed by the acpl-c78a/c780/c784. a diferential output voltage is created on the other side of the acpl-c78a/c780/c784 optical isolation barrier. this diferential output voltage is proportional to the motor current and can be converted to a single-ended signal by using an op-amp as shown in the recommended ap - plication circuit. since common-mode voltage swings of several hundred volts in tens of nanoseconds are common in modern switching inverter motor drives, the acpl-c78a/c780/c784 is designed to ignore very high common-mode transient slew rates (of at least 10 kv/ s). the high cmr capability of the acpl-c78a/c780/c784 isolation amplifer provides the precision and stability needed to accurately monitor motor current in high noise motor control environments, providing for smoother control (less torque ripple) in various types of motor control applications. the product can also be used for general analog signal isolation applications requiring high accuracy, stability, and linearity under similarly severe noise conditions. for general applications, we recommend the acpl-c780 (gain tolerance of 3%) and the acpl-c784 (gain tolerance of 5%). for precision applications avago technologies ofers the acpl-c78a with part-to-part gain tolerance of 1%. the acpl-c78a/c780/c784 utilizes sigma-delta ( -? ) an - alog-to-digital converter technology, chopper stabilized amplifers, and a fully diferential circuit topology. together, these features deliver unequaled isolation- mode noise rejection, as well as excellent ofset and gain accuracy and stability over time and temperature. this performance is delivered in a compact, auto-insertable, stretched so-8 (sso-8) package that meets worldwide regulatory safety standards. features ? 15 kv/ s common-mode rejection at v cm = 1000 v ? compact, auto-insertable stretched so-8 package ? 0.00025 v/v/c gain drift vs. temperature ? 0.3 mv input ofset voltage ? 100 khz bandwidth ? 0.004% nonlinearity ? worldwide safety approval: ul 1577 (5000 vrms/1 min.), csa and iec/en/din en 60747-5-5 ? advanced sigma-delta ( -? ) a/d converter technology ? fully diferential amplifer applications ? motor phase and rail current sensing ? inverter current sensing ? dc bus voltage sensing ? general purpose current sensing and monitoring ? general purpose analog signal isolation functional diagram 1 2 3 4 8 7 6 5 i dd1 v dd1 v in+ v in- gnd1 i dd2 v dd2 v out+ v out- gnd2 + - + - shield
2 pin description pin no. symbol description 1 v dd1 supply voltage for input side (4.5 v to 5.5 v), relative to gnd1 2 v in+ positive input ( 200 mv recommended) 3 v inC negative input (normally connected to gnd1) 4 gnd1 input side ground 5 gnd2 output side ground 6 v outC negative output 7 v out+ positive output 8 v dd2 supply voltage for output side (4.5 v to 5.5 v), relative to gnd2 ordering information acpl-c78a/c780/c784 is ul recognized with 5000 vrms/1 minute rating per ul 1577. part number option (rohs compliant) package surface mount tape& reel iec/en/din en 60747-5-5 quantity acpl-c78a acpl-c780 acpl-c784 -000e stretched so-8 x 80 per tube -060e x x 80 per tube -500e x x 1000 per reel -560e x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example: acpl-c78a-560e to order product of surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval and rohs compliance. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 note 1: v = is 060 or 560; other options are not marked. package outline drawings stretched so-8 package (sso-8) 5.850 0.50 (0.230 0.010) 5 6 7 8 4 3 2 1 dimensions in millimeters and (inches). lead coplanarity = 0.1 mm (0.004 inches). 6.807 0.127 (0.268 0.005) recommended land pattern 12.650 (0.5) 1.905 (0.1) 3.180 0.127 (0.125 0.005) 0.381 0.130 (0.015 0.005) 1.27 0 (0.050) bsg 7 (0.453 0.010) (0.008 0.004) (0.0295 0.010) 0.200 0.100 0.750 0.250 11.50 0.250 (0.063 0.005) 1.590 0.127 (0.018) 0.450 45 v = option code [1] rohs-compliance indicator part number date code c78a v yyww recommended pb-free ir profle recommended refow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used. ul approval under ul 1577, component recognition program up to v iso = 5000 v rms . file e55361. csa approval under csa component acceptance notice #5, file ca 88324. iec/en/din en 60747-5-5 approval with maximum working insulation voltage v iorm = 1414 v peak . regulatory information the acpl-c78a/c780/c784 is approved by the following organizations:
4 insulation and safety related specifcations parameter symbol value units conditions minimum external air gap (external clearance) l(101) 8.0 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (external creepage) l(102) 8.0 mm measured from input terminals to output terminals, shortest distance path along body minimum internal plastic gap (internal clearance) 0.5 mm through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) iec/en/din en 60747-5-5 insulation characteristics (option 060) [1] description symbol value units installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 150 vrms for rated mains voltage 300 vrms for rated mains voltage 450 v rms for rated mains voltage 600 vrms for rated mains voltage 1000 vrms i-iv i-iv i-iv i-iv i-iii climatic classifcation 55/100/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 1414 v peak input to output test voltage, method b v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 2652 v peak input to output test voltage, method a v iorm x 1.5 = v pr , type and sample test, t m = 10 sec, partial discharge < 5 pc v pr 2262 v peak highest allowable overvoltage (transient overvoltage, t ini = 60 sec) v iotm 8000 v peak safety-limiting values (maximum values allowed in the event of a failure) case temperature input current [2] output power [2] t s i s,input p s,output 175 230 600 c ma mw insulation resistance at t s , v io = 500 v r s f 10 9 notes: 1. insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the application. 2. safety-limiting parameters are dependent on ambient temperature. the input current, i s,input , derates linearly above 25 c free-air temperature at a rate of 2.53 ma/c; the output power, p s,output , derates linearly above 25 c free-air temperature at a rate of 4 mw/c.
5 absolute maximum rating parameter symbol min. max. units note storage temperature t s C55 +125 c ambient operating temperature t a C40 +100 c supply voltages v dd1 , v dd2 0 5.5 v steady-state input voltage v in+ , v inC C2 v dd1 + 0.5 v two second transient input voltage v in+ , v inC C6 v output voltages v out+ , v outC C0.5 v dd2 + 0.5 v lead solder temperature 260c for 10 sec., 1.6 mm below seating plane 1 notes: 1. non-halide flux should be used. recommended operating conditions parameter symbol min. max. units note ambient operating temperature t a C40 +85 c supply voltages v dd1 , v dd2 4.5 5.5 v input voltage (linear and accurate) v in+ , v inC C200 +200 mv 1 input voltage (functional) v in+ , vinC C2 2 v
6 dc electrical specifcations unless otherwise noted, all typicals and fgures are at the nominal operating conditions of v in+ = 0, v inC = 0 v, v dd1 = v dd2 = 5 v and t a = 25c; all minimum and maximum specifcations are within the recommended operating conditions. parameter symbol min. typ. max. unit test conditions fig. note input ofset voltage v os C2 0.3 2 mv t a = 25c 1,2,3 input ofset voltage v os C3 3 t a = C40c to +85c 1,2,3 magnitude of input ofset change vs. temperature |dv os /dt a | 3 10 v/c 2 2 gain (acpl-c78a, 1%) g1 7.92 8 8.08 v/v v in+ = C200 mv to +200 mv, t a = 25c 4,5,6 3 gain (acpl-c780, 3%) g3 7.76 8 8.24 v/v v in+ = C200 mv to +200 mv, t a = 25c 4,5,6 3 gain (acpl-c784, 5%) g5 7.6 8 8.4 v/v v in+ = C200 mv to +200 mv, t a = 25c 4,5,6 3 magnitude of v out gain change vs.temperature |dg/dt a | 0.00025 v/v/c 4,5,6 4 v out nonlinearity over 200 mv input voltage nl 200 0.0037 0.35 % v in+ = C200 mv to +200 mv 7,8 5 magnitude of nl 200 change vs. temperature |dnl 200 /dt a | 0.0002 %/c 7,8 5 v out nonlinearity over 100 mv input voltage nl 100 0.0027 0.2 % v in+ = C100 mv to +100 mv 7,8 6 maximum input voltage before v out clipping |v in+ | max 308 mv 9 input side supply current i dd1 11 16 ma v in+ = +400 mv 10 7 output side supply current i dd2 13 16 ma v in+ = C400 mv 10 8 input current i in+ C5 C0.5 a v in+ = 0, v inC = 0 v 11 9 magnitude of input bias current vs.temperature |di in /dt a | 0.45 na/c output low voltage v ol 1.29 v 9 10 output high voltage v oh 3.8 v 9 10 v out output common- mode voltage v ocm 2.2 2.545 2.8 v v out output short-circuit current |i osc | 18.6 ma v out = 0 v or v dd2 11 equivalent input impedance r in 500 k 9 v out output resistance r out 15 input dc common-mode rejection ratio cmrr in 76 db 12
7 ac electrical specifcations unless otherwise noted, all typicals and fgures are at the nominal operating conditions of v in+ = 0, v inC = 0 v, v dd1 = v dd2 = 5 v and t a = 25c; all minimum and maximum specifcations are within the recommended operating conditions. parameter symbol min. typ. max. unit test conditions fig. note small-signal bandwidth (-3 db) f C3 db 50 100 khz v in+ = 200 mvpk-pk sine wave 12,13 rms v out noise v n 31.5 mvrms v in+ = 0 v 13 v in to v out signal delay (50 C 10%) t pd10 2.03 3.3 s v in+ = 0 to 150 mv step, measured at v out node in figure 15 14,15 v in to v out signal delay (50 C 50%) t pd50 3.47 5.6 s v in+ = 0 to 150 mv step, measured at v out node in figure 15 14,15 v in to v out signal delay (50 C 90%) t pd90 4.99 9.9 s v in+ = 0 to 150 mv step, measured at v out node in figure 15 14,15 v out rise/ fall time (10 C 90%) t r/f 2.96 6.6 s v in+ = 0 to 150 mv step, measured at v out node in figure 15 14,15 common mode transient immunity cmti 10 15 kv/ s v cm = 1 kv, t a = 25c 16 14 power supply rejection psr 170 mvrms 15 package characteristics parameter symbol min. typ. max. unit test condition fig. note input-output momentary withstand voltage v iso 5000 vrms rh < 50%, t = 1 min., t a = 25c 16,17 resistance (input-output) r i-o >10 12 v i-o = 500 v dc 18 capacitance (input-output) c i-o 0.5 pf f = 1 mhz 18
8 notes: general note: typical values represent the mean value of all char - acterization units at the nominal operating conditions. typical drift specifcations are determined by calculating the rate of change of the specifed parameter versus the drift parameter (at nominal operating conditions) for each characterization unit, and then averaging the indi - vidual unit rates. the corresponding drift fgures are normalized to the nominal operating conditions and show how much drift occurs as the particular drift parameter is varied from its nominal value, with all other parameters held at their nominal operating values. note that the typical drift specifcations in the tables may difer from the slopes of the mean curves shown in the corresponding fgures. 1. it is recommended to operate with v inC = 0 v (tied to gnd1). limiting v in+ to 100 mv will improve dc nonlinearity and nonlinearity drift. if v inC is brought above v dd1 C 2 v, an internal test mode may be activated. this test mode is for led coupling test and is not intended for customer use. 2. this is the absolute value of input ofset change vs. temperature. 3. gain is defned as the slope of the best-ft line of diferential output voltage (v out+ Cv outC ) vs. diferential input voltage (v in+ Cv inC ) over the specifed input range. 4. this is the absolute value of gain change vs. temperature. 5. nonlinearity is defned as half of the peak-to-peak output deviation from the best-ft gain line, expressed as a percentage of the full-scale diferential output voltage. 6. nl 100 is the nonlinearity specifed over an input voltage range of 100 mv. 7. the input supply current decreases as the diferential input voltage (v in+ Cv inC ) decreases. 8. the maximum specifed output supply current occurs when the diferential input voltage (v in+ Cv inC ) = C200 mv, the maximum recommended operating input voltage. however, the output supply current will continue to rise for diferential input voltages up to approximately C300 mv, beyond which the output supply current remains constant. 9. because of the switched-capacitor nature of the input sigma-delta converter, time-averaged values are shown. 10. when the diferential input signal exceeds approximately 308 mv, the outputs will limit at the typical values shown. 11. short circuit current is the amount of output current generated when either output is shorted to v dd2 or gnd2. 12. cmrr is defned as the ratio of the diferential signal gain (signal applied diferentially between pins 2 and 3) to the common-mode gain (input pins tied together and the signal applied to both inputs at the same time), expressed in db. 13. output noise comes from two primary sources: chopper noise and sigma-delta quantization noise. chopper noise results from chopper stabilization of the output op-amps. it occurs at a specifc frequency (typically 400 khz at room temperature), and is not attenuated by the internal output flter. a flter circuit can be easily added to the external post-amplifer to reduce the total rms output noise. the internal output flter does eliminate most, but not all, of the sigma- delta quantization noise. the magnitude of the output quantization noise is very small at lower frequencies (below 10 khz) and increases with increasing frequency. 14. cmti (common mode transient immunity or cmr, common mode rejection) is tested by applying an exponentially rising/falling voltage step on pin 4 (gnd1) with respect to pin 5 (gnd2). the rise time of the test waveform is set to approximately 50 ns. the amplitude of the step is adjusted until the diferential output (v out+ Cv outC ) exhibits more than a 200 mv deviation from the average output voltage for more than 1s. the acpl-c78a/c780/c784 will continue to function if more than 10 kv/s common mode slopes are applied, as long as the breakdown voltage limitations are observed. 15. data sheet value is the diferential amplitude of the transient at the output of the acpl-c78a/c780/c784 when a 1 vpk-pk, 1 mhz square wave with 40 ns rise and fall times is applied to both v dd1 and v dd2 . 16. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage f6000 vrms for 1 second (leakage detection current limit, i i-o 5 a). this test is performed before the 100% production test for partial discharge (method b) shown in iec/ en/din en 60747-5-5 insulation characteristic table. 17. the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating, refer to the iec/en/din en 60747-5-5 insulation characteristics table and your equipment level safety specifcation. 18. this is a two-terminal measurement: pins 1C4 are shorted together and pins 5C8 are shorted together. figure 1. input ofset voltage test circuit. 0.1 f v dd2 v out 8 7 6 1 3 acpl-c78a acpl-c780 acpl-c784 5 2 4 0.1 f 10 k 10 k v dd1 +15 v 0.1 f 0.1 f -15 v + ? ad624cd gain = 100 0.47 f 0.47 f
9 t a - temperature - c t a - temperature - c 0.6 0.5 0.3 -25 0.8 35 95 0.2 0.7 -55 0.4 5 65 v os - input offset voltage - mv v dd - supply voltage - v 0.37 0.36 0.39 4.75 5.0 0.33 4.5 5.5 5.25 vs. v dd1 vs. v dd2 0.34 0.38 0.35 v os - input offset voltage - mv g - gain - v/v 8.025 8.02 8.015 -35 8.035 25 85 8.01 8.03 -55 5 45 -15 65 figure 3. input ofset vs. supply. figure 4. gain vs. temperature. figure 2. input ofset voltage vs. temperature. figure 5. gain and nonlinearity test circuit. 0.1f v dd2 8 7 6 1 3 acpl-c78a acpl-c780 acpl-c784 5 2 4 0.01 f 10 k 10 k +15 v 0.1 f 0.1 f -15 v + ? ad624cd gain = 4 0.47 f 0.47 f v dd1 13.2 404 v in v out +15 v 0.1 f 0.1 f -15 v + ? ad624cd gain = 10 10 k 0.47 f 0.1 f
10 g - gain - v/v v dd - supply voltage - v 8.028 8.032 4.75 5.0 8.024 4.5 5.5 5.25 8.03 8.026 vs. v dd1 vs. v dd2 nl - nonlinearity - % t a - temperature - c 0.02 0.015 0.005 -25 0.03 35 95 0 0.025 -55 0.01 5 65 nl - nonlinearity - % v dd - supply voltage - v 0.005 4.75 5.0 0.002 4.5 5.5 5.25 0.004 0.003 v o - output voltage - v 2.6 1.8 -0.3 4.2 -0.1 0.1 0.3 1.0 3.4 -0.5 0.5 i dd - supply current - ma v in - input voltage - v v in - input voltage - v v in - input voltage - v 7 -0.3 13 -0.1 0.1 0.3 4 10 -0.5 0.5 i in - input current - a -3 -0.4 0 -0.2 0.2 0.4 -5 -1 -0.6 0.6 -2 -4 0 vs. v dd1 vs. v dd2 v out+ v out? i dd1 , v in+ = +400 mv i dd2 , v in+ = ?400 mv figure 6. gain vs. supply. figure 7. nonlinearity vs. temperature. figure 8. nonlinearity vs. supply. figure 9. output voltage vs. input voltage. figure 10. supply current vs. input voltage. figure 11. input current vs. input voltage.
11 gain - db frequency (hz) -2 1 -4 0 10 100000 -1 -3 1000 100 10000 phase - degrees frequency (hz) -100 50 -300 0 10 100000 -50 -150 1000 -200 -250 100 10000 pd - propagation delay - s t a - temperature - c 3.1 -25 5.5 5 65 95 1.5 4.7 -55 3.9 2.3 35 tpd 10 tpd 50 tpd 90 trise figure 15. propagation delay test circuits. figure 12. gain vs. frequency. figure 13. phase vs. frequency. figure 14. propagation delay vs. temperature. 0.1 f v dd2 v out 8 7 6 1 3 acpl-c78a acpl-c780 acpl-c784 5 2 4 2 k 2 k +15 v 0.1 f 0.1 f -15 v ? + mc34081 0.1 f 10 k 10 k 0.01 f v dd1 v in v in impedance less than 10 ?.
12 application information power supplies and bypassing the recommended supply connections are shown in figure 17. a foating power supply (which in many ap - plications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 v using a simple zener diode (d1); the value of resistor r4 should be chosen to supply sufcient current from the existing foating supply. the voltage from the current sensing resistor (rsense) is applied to the input of the acpl-c78a/ c780/c784 through an rc anti-aliasing flter (r2 and c2). although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. the power supply for the acpl-c78a/c780/c784 is most often obtained from the same supply used to power the power transistor gate drive circuit. if a dedicated supply is required, in many cases it is possible to add an additional winding on an existing transformer. otherwise, some sort of simple isolated supply can be used, such as a line powered transformer or a high-frequency dc-dc converter. an inexpensive 78l05 three-terminal regulator can also be used to reduce the foating supply voltage to 5 v. to help attenuate high-frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass flter with the regulators input bypass capacitor. as shown in figure 18, 0.1 f bypass capacitors (c1, c2) should be located as close as possible to the pins of the figure 16. cmti test circuits. 0.1 f v dd2 v out 8 7 6 1 3 acpl-c78a acpl-c780 acpl-c784 5 2 4 2 k 2 k 78l05 +15 v 0.1 f 0.1 f -15 v ? + mc34081 150 pf in out 0.1 f 0.1 f 9 v pulse gen. v cm + ? 10 k 10 k 150 pf acpl-c78a/c780/c784. the bypass capacitors are required because of the high-speed digital nature of the signals inside the acpl-c78a/c780/c784. a 0.01 f bypass capacitor (c2) is also recommended at the input due to the switched-capacitor nature of the input circuit. the input bypass capacitor also forms part of the anti- aliasing flter, which is recommended to prevent high- frequency noise from aliasing down to lower frequencies and interfering with the input signal. the input flter also performs an important reliability function C it reduces transient spikes from esd events fowing through the current sensing resistor. pc board layout the design of the printed circuit board (pcb) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. in addition, the layout of the pcb can also afect the isolation transient immunity (cmti) of the acpl-c78a/c780/c784, due primarily to stray capacitive coupling between the input and the output circuits. to obtain optimal cmti performance, the layout of the pc board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the pc board does not pass directly below or extend much wider than the body of the acpl-c78a/c780/c784.
13 figure 18. recommended application circuit. figure 17. recommended supply and sense resistor connections. acpl-c78a acpl-c780 acpl-c784 c1 0.1 f r2 39 ? gate drive circuit floating power supply * * * hv+ * * * hv- * * * ? + r sense motor c2 0.01 f d1 5.1 v ? + r1 0.1 f v dd2 (+5 v) v dd1 v out 8 7 6 1 3 u2 5 2 4 r1 2.00 k +15 v c8 0.1 f 0.1 f -15 v ? + tl032a r3 10.0 k acpl-c78a acpl-c780 acpl-c784 c4 r4 10.0 k c6 150 pf u3 u1 78l05 in out c1 c2 0.01 f r5 68 gate drive circuit positive floating supply hv+ * * * hv- ? + r sense motor c5 150 pf 0.1 f 0.1 f c3 c7 r2 2.00 k * * * * * * gnd1 gnd2 gnd2 gnd2 gnd2 figure 19. example printed circuit board layout. to gnd1 to v dd1 r5 c3 c4 to v dd2 to gnd2 v out+ v out? to r sense+ to r sense? c2 note: drawing not to scale u2 acpl - c78a/c780/c784
14 figure 20. motor output horsepower vs. motor phase current and supply voltage. current sensing resistors the current sensing resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely afect operation), and reasonable tolerance (to maintain overall circuit accuracy). choosing a particular value for the resistor is usually a compromise between minimiz - ing power dissipation and maximizing accuracy. smaller sense resistance decreases power dissipation, while larger sense resistance can improve circuit accuracy by utilizing the full input range of the acpl-c78a/c780/c784. the frst step in selecting a sense resistor is determining how much current the resistor will be sensing. the graph in figure 20 shows the rms current in each phase of a three- phase induction motor as a function of average motor output power (in horsepower, hp) and motor drive supply voltage. the maximum value of the sense resistor is deter - mined by the current being measured and the maximum recommended input voltage of the isolation amplifer. the maximum sense resistance can be calculated by taking the maximum recommended input voltage and dividing by the peak current that the sense resistor should see during normal operation. for example, if a motor will have a maximum rms current of 10 a and can experience up to 50% overloads during normal operation, then the peak current is 21.1 a (=10 x 1.414 x 1.5). assuming a maximum input voltage of 200 mv, the maximum value of sense re - sistance in this case would be about 10 m . the maximum average power dissipation in the sense resistor can also be easily calculated by multiplying the sense resistance times the square of the maximum rms current, which is about 1 w in the previous example. if the power dissipation in the sense resistor is too high, the re - sistance can be decreased below the maximum value to decrease power dissipation. the minimum value of the sense resistor is limited by precision and accuracy require - ments of the design. as the resistance value is reduced, the output voltage across the resistor is also reduced, which means that the ofset and noise, which are fxed, become a larger percentage of the signal amplitude. the selected value of the sense resistor will fall somewhere between the minimum and maximum values, depending on the particular requirements of a specifc design. when sensing currents large enough to cause signifcant heating of the sense resistor, the temperature coefcient (tempco) of the resistor can introduce nonlinearity due to the signal dependent temperature rise of the resistor. the efect increases as the resistor-to-ambient thermal resis - tance increases. this efect can be minimized by reducing the thermal resistance of the current sensing resistor or by using a resistor with a lower tempco. lowering the thermal resistance can be accomplished by reposition - ing the current sensing resistor on the pc board, by using larger pc board traces to carry away more heat, or by using a heat sink. for a two-terminal current sensing resistor, as the value of resistance decreases, the resistance of the leads become a signifcant percentage of the total resistance. this has two primary efects on resistor accuracy. first, the efective resistance of the sense resistor can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the leads during assembly (these issues will be discussed in more detail shortly). second, the leads are typically made from a material, such as copper, which has a much higher tempco than the material from which the resistive element itself is made, resulting in a higher tempco overall. both of these efects are eliminated when a four-terminal current sensing resistor is used. a four-terminal resistor has two additional terminals that are kelvin connected directly across the resistive element itself; these two terminals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load current. because of the kelvin connection, any voltage drops across the leads carrying the load current should have no impact on the measured voltage. when laying out a pc board for the current sensing resistors, a couple of points should be kept in mind. the kelvin connections to the resistor should be brought together under the body of the resistor and then run very close to each other to the input of the acpl-c78a/c780/ c784; this minimizes the loop area of the connection and reduces the possibility of stray magnetic felds from inter - fering with the measured signal. if the sense resistor is not located on the same pc board as the acpl-c78a/c780/ c784 circuit, a tightly twisted pair of wires can accomplish the same thing. motor phase current - a (rms) 15 5 40 10 25 30 0 35 0 35 25 10 20 440 v 380 v 220 v 120 v 30 20 5 15 motor output power - horsepower
15 also, multiple layers of the pc board can be used to increase current carrying capacity. numerous plated- through vias should surround each non-kelvin terminal of the sense resistor to help distribute the current between the layers of the pc board. the pc board should use 2 or 4 oz. copper for the layers, resulting in a current carrying capacity in excess of 20 a. making the current carrying traces on the pc board fairly large can also improve the sense resistors power dissipation capability by acting as a heat sink. liberal use of vias where the load current enters and exits the pc board is also recommended. note: please refer to avago technologies application note 1078 for additional information on using isolation amplifers. sense resistor connections the recommended method for connecting the acpl-c78a/c780/c784 to the current sensing resistor is shown in figure 18. v in+ (pin 2 of the acpl-c78a/c780/ c784) is connected to the positive terminal of the sense resistor, while v in- (pin 3) is shorted to gnd1 (pin 4), with the power-supply return path functioning as the sense line to the negative terminal of the current sense resistor. this allows a single pair of wires or pc board traces to connect the acpl-c78a/c780/c784 circuit to the sense resistor. by referencing the input circuit to the negative side of the sense resistor, any load current induced noise transients on the resistor are seen as a common-mode signal and will not interfere with the current-sense signal. this is important because the large load currents fowing through the motor drive, along with the parasitic induc - tances inherent in the wiring of the circuit, can generate both noise spikes and ofsets that are relatively large compared to the small voltages that are being measured across the current sensing resistor. if the same power supply is used both for the gate drive circuit and for the current sensing circuit, it is very important that the connection from gnd1 of the acpl-c78a/c780/ c784 to the sense resistor be the only return path for supply current to the gate drive power supply in order to eliminate potential ground loop problems. the only direct con nection between the acpl-c78a/c780/c784 circuit and the gate drive circuit should be the positive power supply line. output side the op-amp used in the external post-amplifer circuit should be of sufciently high precision so that it does not contribute a signifcant amount of ofset or ofset drift relative to the contribution from the isolation amplifer. generally, op-amps with bipolar input stages exhibit better ofset performance than op-amps with jfet or mosfet input stages. in addition, the op-amp should also have enough band- width and slew rate so that it does not adversely afect the response speed of the overall circuit. the post-amplifer circuit includes a pair of capacitors (c5 and c6) that form a single-pole low-pass flter; these capacitors allow the bandwidth of the post-amp to be adjusted independently of the gain and are useful for reducing the output noise from the isola-tion amplifer. many diferent op-amps could be used in the circuit, including: tl032a, tl052a, and tlc277 (texas instruments), lf412a (national semi - conductor). the gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate cmrr and adequate gain tolerance for the overall circuit. resistor networks can be used that have much better ratio toler - ances than can be achieved using discrete resistors. a resistor network also reduces the total number of compo - nents for the circuit as well as the required board space. frequently asked questions about the acpl-c78a/c780/c784 1. the basics 1.1. why should i use the acpl-c78a/c780/c784 for sensing current when hall-efect sensors are available which dont need an isolated supply voltage? available in an auto-insertable, stretched so-8 package, the acpl-c78a/c780/c784 is smaller than and has better linearity, ofset vs. temperature and common mode rejection (cmr) performance than most hall-efect sensors. additionally, often the required input-side power supply can be derived from the same supply that powers the gate-drive optocoupler. 2. sense resistor and input flter 2.1. where do i get 10 m resistors? i have never seen one that low. although less common than values above 10 , there are quite a few manufacturers of resistors suitable for measuring currents up to 50 a when combined with the acpl-c78a/c780/c784. example product information may be found at vishay's web site (http://www.vishay.com) and isoteks web site (http://www.isotekcorp.com). 2.2. should i connect both inputs across the sense resistor instead of grounding v in- directly to pin 4? this is not necessary, but it will work. if you do, be sure to use an rc flter on both pin 2 (v in+ ) and pin 3 (v in- ) to limit the input voltage at both pads.
16 2.3. do i really need an rc flter on the input? what is it for? are other values of r and c okay? the input anti-aliasing flter (r=39 , c=0.01 f) shown in the typical application circuit is recom - mended for fltering fast switching voltage transients from the input signal. (this helps to attenuate higher signal frequencies which could otherwise alias with the input sampling rate and cause higher input ofset voltage.) some issues to keep in mind using diferent flter resistors or capacitors are: 1. filter resistor: input bias current for pins 2 and 3: this is on the order of 500 na. if you are using a single flter resistor in series with pin 2 but not pin 3 the ixr drop across this resistor will add to the ofset error of the device. as long as this ir drop is small compared to the input ofset voltage there should not be a problem. if larger-valued resistors are used in series, it is better to put half of the resistance in series with pin 2 and half the resistance in series with pin 3. in this case, the ofset voltage is due mainly to resistor mismatch (typically less than 1% of the resistance design value) multiplied by the input bias. 2. filter resistor: the equivalent input resistance for acpl-c78a/c780/c784 is around 500 k . it is therefore best to ensure that the flter resistance is not a signifcant percentage of this value; otherwise the ofset voltage will be increased through the resistor divider efect. [as an example, if r flt = 5.5 k , then v os = (vin * 1%) = 2 mv for a maximum 200 mv input and v os will vary with respect to vin.] 3. the input bandwidth is changed as a result of this diferent r-c flter confguration. in fact this is one of the main reasons for changing the input-flter r-c time constant. 4. filter capacitance: the input capacitance of the acpl-c78a/c780/c784 is approximately 1.5 pf. for proper operation the switching input-side sampling capacitors must be charged from a relatively fxed (low impedance) voltage source. therefore, if a flter capacitor is used it is best for this capacitor to be a few orders of magnitude greater than the c input (a value of at least 100 pf works well.) 2.4. how do i ensure that the acpl-c78a/c780/c784 is not destroyed as a result of short circuit conditions which cause voltage drops across the sense resistor that exceed the ratings of the acpl- c78a/c780/c784s inputs? select the sense resistor so that it will have less than 5 v drop when short circuits occur. the only other require - ment is to shut down the drive before the sense resistor is damaged or its solder joints melt. this ensures that the input of the acpl-c78a/c780/c784 can not be damaged by sense resistors going open-circuit. 3. isolation and insulation 3.1. how many volts will the acpl-c78a/c780/c784 withstand? the momentary (1 minute) withstand voltage is 5000 v rms per ul 1577 and csa component acceptance notice #5. 4. accuracy 4.1. can the signal to noise ratio be improved? yes. some noise energy exists beyond the 100 khz bandwidth of the acpl-c78a/c780/c784. additional fltering using diferent flter r,c values in the post-am - plifer application circuit can be used to improve the signal to noise ratio. for example, by using values of r3 = r4 = 10 k , c5 = c6 = 470 pf in the application circuit the rms output noise will be cut roughly by a factor of 2. in applications needing only a few khz bandwidth even better noise performance can be obtained. the noise spectral density is roughly 500 nv/sqrt(hz) below 20 khz (input referred). 4.2. does the gain change if the internal led light output degrades with time? no. the led is used only to transmit a digital pattern. avago technologies has accounted for led degrada - tion in the design of the product to ensure long life. 5. power supplies and start-up 5.1. what are the output voltages before the input side power supply is turned on? v out+ is close to 1.29 v and v outC is close to 3.80 v. this is equivalent to the output response at the condition that led is completely of. 5.2. how long does the acpl-c78a/c780/c784 take to begin working properly after power-up? within 1 ms after v dd1 and v dd2 powered the device starts to work. but it takes longer time for output to settle down completely. in case of the ofset mea - surement while both inputs are tied to ground there is initially v os adjustment (about 60 ms). the output completely settles down in 100 ms after device powering up. 6. miscellaneous 6.1. how does the acpl-c78a/c780/c784 measure negative signals with only a +5 v supply? the inputs have a series resistor for protection against large negative inputs. normal signals are no more than 200 mv in amplitude. such signals do not forward bias any junctions sufciently to interfere with accurate operation of the switched capacitor input circuit.
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-1436en - march 26, 2013

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